Embodiments of the invention were motivated in addressing trade-offs in attaining high device on-current (Ion) at the expense of undesired current leakage in recessed access devices.
A recessed access device is a field effect transistor having its gate construction buried within a trench formed in semiconductive material. The gate construction includes a gate insulator which lines the trench and conductive gate material within the trench laterally inward of the gate insulator. A source/drain region is formed in outermost regions of the semiconductive material on each of opposing sides of the trench. When the two source/drain regions are at different voltages and a suitable voltage is applied to the conductive gate material, current (Ion) flows through the semiconductive material between the source/drain regions along the trench sidewalls and around the base of the trench (i.e., a conductive channel forms through which current flows between the two source/drain regions). Voltage of the source/drain regions is typically controlled through a respective conductive via that makes electrically coupling contact with the respective source/drain region. To minimize contact resistance, the elevationally outermost portions of the source/drain regions may be provided with a high conductivity dopant implant, for example phosphorus (for n-type) implanted at 1 to 8 keV at a dose of 1×1014 atoms/cm2 to 4×1014 atoms/cm2 to provide a conductivity-increasing implant of greater than 1×1020 atoms/cm3. This renders the elevationally outermost portion of the source/drain region highly conductive, thereby reducing contact resistance but at the expense of increasing gate induced drain leakage (GIDL) or off current (Ioff). GIDL is a negative attribute associated with field effect transistors and can be problematic with recessed access devices or other devices or applications where leakage is a concern. For example, DRAM access devices can suffer from charge leakage due to increase in GIDL. High dose implants can increase Ion but also can increase GIDL.
As device dimensions shrink in the ever-continuing goal of fabricating denser integrated circuitry, the available area for conductive contact of vias shrinks. This raises both contact resistance and contact-via resistance. Further where the via is made of conductively doped polysilicon, dopant diffusion from that via during subsequent thermal cycles raises GIDL.
While the invention was motivated in addressing the above issues, it is not so limited.